The relentless pursuit of faster and more energy-efficient computing has hit a fundamental physical barrier known as the Boltzmann limit, which constrains the minimum energy required to switch a conventional transistor. However, a team at The Hong Kong Polytechnic University (PolyU) has engineered a novel tunnelling field-effect transistor (TFET) that overcomes this limit, offering a path to ultra-low-power, high-performance integrated circuits essential for emerging AI chips and advanced semiconductor applications.
Led by Prof. Jianhua Hao, Head of the Department of Physics and Materials and Chair Professor of Materials Physics and Devices at PolyU, the research was conducted in collaboration with the National University of Singapore, The Hong Kong University of Science and Technology, Peking University, and the Singapore University of Technology and Design. The findings were published in the prestigious scientific journal Science.
Conventional transistors operate through thermionic emission, a process that requires a minimum gate voltage of 60 millivolts (mV) to switch at room temperature. This 'Boltzmann limit' makes subthreshold swing (SS) values below 60 mV per decade physically impossible, thereby restricting the energy efficiency of traditional transistors. By adopting quantum tunnelling, the PolyU-developed TFET breaks through this boundary, enabling high-performance electronics that consume far less power.
Prof. Hao explained, 'By adopting quantum tunnelling, our TFET breaks through this boundary, paving the way for ultra-low-power, high-performance integrated circuits essential for emerging AI chips and advanced semiconductor applications.'
The team created an ultra-thin heterostructure of alternating layers of 2D bismuth and indium selenide using pulsed laser deposition. Through precise control of the layer structure, the normally semi-metallic bismuth transforms into a semiconductor in its 2D form, allowing charge carriers to tunnel efficiently into indium selenide via quantum tunnelling. The resulting TFET achieved SS values well below the 60 mV per decade limit.
Operating at room temperature on silicon substrates, the device required a gate-voltage range of only 160 mV, far lower than the 800 mV needed by conventional devices. This significant reduction in operating voltage translates to substantial energy savings, a critical factor for battery-powered devices and large-scale data centres.
The device also resolved a long-standing challenge in experimental TFETs by delivering a high output current alongside an exceptionally high ON/OFF current ratio. This combination allows the TFET to drive multiple downstream logic gates, diminishing circuit delay and enabling more complex integrated circuits.
This breakthrough has profound implications for the semiconductor industry. As AI models become more sophisticated, the demand for energy-efficient computing grows. The PolyU TFET could lead to a new generation of AI chips that are faster, more powerful, and consume significantly less energy. It also offers a viable path to continue Moore's law, which has been slowing due to physical limitations.
Prof. Hao's team is now exploring further optimisations and potential integration with existing CMOS technology. The research represents a significant step forward in the quest for next-generation microelectronics.
